1. Field of the Invention
The present invention relates in general to a method of making integrated circuits (ICs), and more particularly to a method of forming a self-aligned contact of a dynamic random access memory (DRAM) cell. The method improves the electrical connection between a substrate and a wireline by improving the process of etching the self-aligned contact.
2. Description of the Related Art
In the conventional manufacturing process of DRAM cells, after a metal-oxide-semiconductor (MOS) transistor is formed, the forming of insulating layers, the etching of contact windows, and the construction of interconnections are successive and important processes. A widely used technique, known as the self-aligned contact (SAC) technique, is typically used to connect a substrate and a wireline together. The SAC technique further includes the planarization of an upper insulation layer.
FIGS. 1 through 6 illustrate the conventional manufacturing process of forming a self-aligned contact for a DRAM cell. Referring to FIG. 1, a substrate 11 having a metal-oxide-semiconductor (MOS) transistor thereon is illustrated. The MOS transistor includes a gate 13 of doped polysilicon, and source/drain regions 16a, 16b. A gate oxide layer 12 is formed under the gate 13. A cap oxide layer 14 is formed on the gate 13. A spacer 15 is formed on the sidewall of the gate 13. The source/drain regions 16a, 16b have a lightly doped drain structure (LDD). Further, other components of the DRAM cell are formed on the substrate 11, for example, a field oxide layer 17, wirelines 18, a cap oxide layer 19 formed on a respective wireline 18, and a spacer 20 located around the respective wireline 18. An interpoly dielectric (IPD) layer 21 is deposited over the structure described above. The IPD layer 21 is preferably comprised of silicon oxide having a thickness of between 1500 .ANG. and 2500 .ANG..
Referring to FIG. 2, a silicon nitride layer 22 is deposited over the IPD layer 21 using chemical vapor deposition (CVD) to a thickness of between 300 .ANG. and 600 .ANG.. Then, a thicker oxide layer 23 is deposited over the silicon nitride layer 22 using CVD to a thickness of between 5000 .ANG. and 8000 .ANG.. The oxide layer 23 is planarized by etching back. Alternatively, the planarized oxide layer 23 can be replaced with a layer of borophosphosilicate glass (BPSG) deposited by CVD which is planarized by reflow. A layer of photoresist 24 is spun-coated on the top of the planarized oxide layer 23, and then developed and fixed, leaving the region above the source/drain region 16a exposed.
Referring to FIG. 3, using the layer of photoresist 24 as a mask, the oxide layer 23 is etched away. The traditional method of etching the planarized oxide layer 23 uses the silicon nitride layer 22 as a stop layer. The oxide layer 23 is etched using anisotropic dry etching, as indicated by the arrows 25 in FIG. 3. Because of the planarization of the oxide layer 23, the thickness of the oxide layer 23 above the source/drain region 16a is not uniform. Further, dry etching has a low selectivity (the dry etching selectivity rate of nitride to oxide is normally 1:10.about.1:12). As such, over-etching occurs easily. For example, the etching process may etch a portion of the stop layer 22, as shown by the dotted line region 26 in FIG. 3; or else, some residues may remain after the etching process is completed, such as the residuary silicon oxide 27 shown in FIG. 3.
The etching of the silicon nitride layer 22 and the IPD layer 21 is performed successively using conventional anisotropic dry etching. Because of spacers 15, 20 and cap oxide layers 14, 19, the etching processes described above will self align with the source/drain region 16a to form a contact window 29, without etching the regions of the gate 13 or the wirelines 18. Because of residues formed, during the previous process, on the bottom of the contact window 29, that is, on the surface of the source/drain region 16a, some etching residues 28 may remain, as shown in FIG. 4. Then, the photoresist 24 is stripped to form the structure shown in FIG. 4.
Referring to FIG. 5, a doped polysilicon layer 30 is deposited over the structure shown in FIG. 4. Then, a photoresist layer 31 is formed on the doped polysilicon layer 30 using a conventional photolithography process to cover the upper region of the contact window 29. The polysilicon layer 30 is etched using anisotropic dry etching, as indicated by the arrow 32 in FIG. 5.
Referring to FIG. 6, a wireline 33 is formed by stripping the photoresist layer 31 to connect the source/drain region 16a. Thus, the entire manufacturing process of the self-aligned contact is performed.
Due to the low selectivity of anisotropic dry etching used in the known manufacturing processes, and because over-etching of the silicon nitride layer 22 is to be avoided, the etching of the oxide silicon layer 23 results in residues. The residues will narrow the self-aligned contact window 29, resulting, in a possible disconnection between the wireline 33 and the source/drain region 16a.